School of Engineering Computer Engineering MASC




Any area in Computer Architecture. For time reasons, main research has focussed in performance and power. This page is a quick summary, check the publications for a more detailed description.
  • Productive Hardware Design: livehd is a new compiler infrastructure to support more productive hardware design. There are many aspects to this area like incremental hardware compilation, parallel flows, support multiple hardware languages, simulation, synthesis...
    • Architectural Simulator: The current maintained version is esesc. Before this release, we actively worked developing SESC. If you liked sesc, your are going to love ESESC.
    • Complexity: Microprocessor design complexity is growing rapidly. As a result, current development costs for top of the line processors are staggering, and are doubling every 4 years. The goal of the MASC complexity group is to understand, estimate, and reduce processor design complexity. We are developing complexity metrics to understand and estimate processor design complexity. At the same time, we planning approaches to reduce processor design complexity.
    • SCOORE: Santa Cruz Out-of-Order Risc Engine. At Santa Cruz we are developing an out-of-order SPARC V8 processor. This processor is synthesizable on FPGAs and ASIC.
    • Infrared Thermal Measurement Setup: Temperature is a key component for computer architects. Our group has developed an infrared thermal measurement setup with infrared cameras capable of measuring of-the-shelf systems. We have successfully cool down chips with over 200 Watts power consumption. Some videos are available in the thermal page.
    • Speculative Multithreading or Thread-Level Speculation: Speculative Multithreading or Thread-Level Speculation has been proposed as a technique to speed up hard-to-analyze applications by speculatively running code fragments in parallel. It consist in extracting tasks from a sequential code and executing them in parallel, hoping not to violate sequential semantics. The control flow of the sequential code imposes a task order and a data dependence relation. As tasks execute, special hardware support checks that no cross-task dependence is violated. If any is, the incorrect tasks are squashed, any polluted state is repaired, and the tasks are re-executed.
    • Low Power: Energy consumption is a crucial parameter in processor design. Proposal of a unified framework to handle energy consumption and temperature management in a unified manner. Also some low power techniques in caches and instruction window organizations.
    • Out-of-order Processors: Checkpointed early resource recycling (Cherry) mechanism that decouples resource recycling and instruction retirement. The resulting processor has more efficient resource utilization, which leads to performance improvements.
    • Intelligent Memories: Energy, performance, and programmability issues in Intelligent Memories or processor-in-memory.
    • Compilers: Work with gcc to developed a Speculative Multithreading compiler.