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News Blog

2018-02-09 HPCA conference call for papers
Papers are due on 2017-08-01.
More information on HPCA

HPCA 2017

2017-09-01 Advanced Logic Synthesis book chapter titled Automated Pipeline Transformations with Fluid Pipelines paper accepted
Rafael T. Possignolo and Elnaz Ebrahimi and Haven Skinner and Jose Renau. In Reis, André Inácio, Drechsler, Rolf (Eds.), Advanced Logic Synthesis (Springer), 2018.
2017-06-01 Anubis: A new benchmark for incremental synthesis paper accepted
Rafael Trapani Possignolo, Nursultan Kabylkas, and Jose Renau, International Workshop Logic and Synthesis (IWLS), June 2017.
2017-06-01 LiveSynth: Towards an Interactive Synthesis Flow paper accepted
Rafael Trapani Possignolo, and Jose Renau, Design Automation Conference (DAC), June 2017.
2017-05-01 Timing Speculative SRAM paper accepted
Elnaz Ebrahimi, Matthew Guthaus, and Jose Renau, International Symposium on Circuits and Systems (ISCAS), May 2017.
2017-05-01 Level Shifter Design for Voltage Stacking paper accepted
Elnaz Ebrahimi, Rafael Trapani Possignolo, and Jose Renau, International Symposium on Circuits and Systems (ISCAS), May 2017.
2016-08-21 LiveSynth: Towards an Interactive Synthesis Flow paper accepted
Rafael Trapani Possignolo, Jose Renau, Hot Chips A Symposium on High Performance Chips (HotChips poster), August 2016.
2016-07-01 Overhead of Deoptimization Checks in the V8 JavaScript Engine paper accepted
Gabriel Southern and Jose Renau, International Symposium on Workload Characterization (IISWC), July 2016.
2016-06-06 Fluid Pipelines: Elastic Circuitry meets Out-of-Order Execution paper accepted
Rafael Trapani Possignolo, Elnaz Ebrahimi, Haven Skinner, and Jose Renau, International Conference on Computer Design (ICCD), June 2016.
2016-06-01 Fluid Pipelines: Elasticity without Throughput Penalty paper accepted
Rafael Trapani Possignolo, Elnaz Ebrahimi, Haven Skinner, and Jose Renau, International Workshop on Logic and Synthesis (IWLS), April 2016.
2016-05-01 SRAM Voltage Stacking paper accepted
Elnaz Ebrahimi, Rafael Trapani Possignolo, and Jose Renau, International Symposium on Circuits and Systems (ISCAS), May 2016.
2016-04-01 Analysis of PARSEC Workload Scalability paper accepted
Gabriel Southern and Jose Renau, International Symposium on Performance Analysis of Systems and Software (ISPASS), April 2016.
2016-03-01 LiveSim: Going Live with Microarchitecture Simulation paper accepted
Sina Hassani, Gabriel Southern and Jose Renau, International Symposium on High-Performance Computer Architecture (HPCA), February 2016.
2015-07-01 NSF SHF Cascode Supporting and Leveraging Voltage Stacking in Future Microprocessors ($285K)

NSF grant with Michael Huang on voltage stacking

2015-10-10 GPU NTC Process Variation Compensation with Voltage Stacking paper accepted
Rafael Trapani Possignolo, Ehsan Ardestani, Alamelu Sankaranarayanan, Jose Luis Briz, Jose Renau, International Conference on Parallel Architectures and Compilation Techniques (PACT poster), October 2015.
2015-06-01 Deconstructing PARSEC Scalability paper accepted
Gabriel Southern and Jose Renau, Workshop on Duplicating, Deconstructing and Debunking (WDDD), 2015.
2015-11-10 Managing Mismatches in Voltage Stacking with CoreUnfolding paper accepted
Ehsan K. Ardestani, Rafael Trapani Possignolo, Jose Luis Briz, and Jose Renau, ACM's Transactions on Architecture and Code Optimization (TACO), September 2015.
2015-05-01 Section Based Program Analysis to Reduce Overhead of Detecting Unsynchronized Thread Communication paper accepted
Madan Das, Gabriel Southern and Jose Renau, ACM's Transactions on Architecture and Code Organization (TACO), 2015.
2015-02-01 Section Based Program Analysis to Reduce Overhead of Detecting Unsynchronized Thread Communication paper accepted
Madan Das, Gabriel Southern, and Jose Renau, 20th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP Poster), February 2015
2013-04-01 Deterministic Scaling paper accepted
Gabriel Southern, Madan Das, and Jose Renau, Workshop on Determinism and Correctness in Parallel Programming (WODET), March 2013.
2013-04-01 Reducing Logging Overhead for Deterministic Execution paper accepted
Madan Das, Gabriel Southern, and Jose Renau, Workshop on Determinism and Correctness in Parallel Programming (WODET), March 2013.
2013-12-01 Power Blurring: Fast Static and Transient Thermal Analysis Method for Packaged Integrated Circuits and Power Devices paper accepted
Amirkoushyar Ziabari, Je-Hyoung Park, Ehsan K. Ardestani, Jose Renau, Sung-Mo Kang, and Ali Shakouri IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2013.
2012-11-10 Intel Gift

Intel Xeon donation for new cluster

2013-09-12 NSF XPS Cooperative Deterministic Concurrency ($750K)

NSF grant with Cormac on simplifying parallel programming

2013-07-12 NSF CSR Rethinking the Memory Hierarchy ($500K)

NSF grant to build more efficient and simpler memory hierarchies

2013-08-21 ESESC A Fast Performance, Power, and Temperature Multicore Simulator paper accepted
Ehsan K.Ardestani, Gabriel Southern, Jason Doung, Elnaz Ebrahimi, Jose Renau, Hot Chips A Symposium on High Performance Chips (HotChips poster), August 2013.
2013-08-15 An Energy Efficient GPGPU Memory Hierarchy with Tiny Incoherent Caches paper accepted
Alamelu Sankaranarayanan, Ehsan K.Ardestani, Jose Luis Briz, and Jose Renau, International Symposium on Low Power Electronics and Design (ISLPED), September 2013.
2013-08-01 Sampling in Thermal Simulation of Processors: Measurement, Characterization, and Evaluation paper accepted
Ehsan K.Ardestani, Francisco J. Mesa-Martinez , Gabriel Southern , Elnaz Ebrahimi , Jose Renau IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), August 2013.
2013-02-15 ESESC: A Fast Multicore Simulator Using Time-Based Sampling paper accepted
Ehsan K.Ardestani, and Jose Renau, International Symposium on High-Performance Computer Architecture (HPCA), February 2013.
2012-08-01 Two new PhD Students (Rafael and Daphne)
2012-07-12 NSF CRI Thermal Simulation ($290K)

NSF Fast Performance, Power and Thermal Modeling for Heterogenous System

2011-09-10 NSF CRI Fabrication Multicore Research ($120K)

NSF Prototyping Platfform to Enable Power-Centric Multicore Research

2012-08-01 Thermal-Aware Sampling in Architectural Simulation paper accepted
Ehsan K.Ardestani, Elnaz Ebrahimi, Gabriel Southern, and Jose Renau, International Symposium on Low Power Electronics and Design (ISLPED), August 2012.
2012-03-11 Enabling Power Density and Thermal-Aware Floorplanning paper accepted
Ehsan K. Ardestani, Amirkoushyar Ziabari, Ali Shakouri, and Jose Renau, 28th Annual Thermal Measurement, Modeling and Management Symposium (SEMITHERM), March 2012.
2012-06-09 ISCA conference call for papers
Papers are due on 2011-10-14.
More information on ISCA

ISCA 2012

2011-05-21 ReRack: Power Simulation for Data Centers with Renewable Energy Generation paper accepted
Michael Brown, and Jose Renau, GreenMetrics 2011,held in conjunction SIGMETRICS 2011, June 2011.
2012-04-03 ASPLOS conference call for papers
Papers are due on 2011-07-25.
More information on ASPLOS

ASPLOS 2012

2011-03-03 New blog in computer architecture

New computer architecture blog

2011-03-03 Releasing Efficient Beta Cores to Market Early paper accepted
Sangeetha Sudhakrishnan, Rigo Dicochea, and Jose Renau, International Symposium on Computer Architecture (ISCA), June 2011.
2011-06-12 HotCloud conference call for papers
Papers are due on 2011-03-07.
More information on HotCloud

HotCould Workshop

2011-03-11 Fast Thermal Simulators for Architecture Level Integrated Circuit Design paper accepted
Amirkoushyar Ziabari, Ehsan K. Ardestani, Jose Renau, and Ali Shakouri, 27th Annual Thermal Measurement, Modeling and Management Symposium (SEMITHERM), March 2011.
2011-03-17 A Design Time Simulator for Computer Architects paper accepted
Sangeetha Sudhakrishnan, Francisco J. Mesa-Martinez, and Jose Renau, IEEE International Symposium on Quality Electronic Design (ISQED), March 2011. (Best paper award)
2010-12-22 ICS conference call for papers
Papers are due on 2011-01-14.
More information on ICS

International Conference on Supercomputing

2010-10-15 AMD Gift

AMD Magny-Cours for our cluster

2010-08-22 ISCA conference call for papers
Papers are due on 2010-11-15.
More information on ISCA

International Symposium on Computer Architecture

2010-05-01 HPCA conference call for papers
Papers are due on 2010-08-27.
More information on HPCA

International Symposium on High-Performance Computer Architecture

2010-05-01 ASPLOS conference call for papers
Papers are due on 2010-07-26.
More information on ASPLOS

International Conference on Archtectural Support for Programing Languages and Operating Systems'

2010-01-22 MICRO conference call for papers
Papers are due on 2010-06-11.
More information on MICRO

International Symposium on Microarchitecture

2010-01-27 ICCAD conference call for papers
Papers are due on 2010-04-19.
More information on ICCAD

International Conference on Computer-Aided Design

2010-01-10 ISLPED conference call for papers
Papers are due on 2010-03-05.
More information on ISLPED

International Symposium on Low Power Electronics and Design

2010-01-10 PACT conference call for papers
Papers are due on 2010-03-20.
More information on PACT

Parallel Architectures and Compilation Technique

2010-01-10 HOTCHIPS conference call for papers
Papers are due on 2010-03-23.
More information on HOTCHIPS

A Symposium on High-Performance Chips

2010-12-10 Real-time control for Keck Observatory next-generation adaptive optics paper accepted
Marc Reinig, Donald Gavel, Ehsan Ardestani, Jose Renau, Proceedings of the SPIE, 2010.
2010-03-17 Characterizing Processor Thermal Behavior paper accepted
Francisco J. Mesa-Martinez, Ehsan Ardestani, and Jose Renau, Fifteenth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2010.
2010-02-21 Cooling Solutions for Processor Infrared Thermography paper accepted
Ehsan Ardestani, Francisco J. Mesa-Martinez, and Jose Renau, 26th Annual Thermal Measurement, Modeling and Management Symposium (SEMITHERM), February 2010.
2009-08-21 SOI, Interconnect, Package, and Mainboard Thermal Characterization paper accepted
Joseph Nayfach-Battilana and Jose Renau, International Symposium on Low Power Electronics and Design (ISLPED), August 2009 (poster paper).
2009-07-22 Measuring and Modeling Variability using Low-Cost FPGAs paper accepted
Michael Brown, Cyrus Bazeghi, Matthew R. Gutthaus, and Jose Renau, Workshop on Modeling, Benchmarking and Simulation (MOBS), held inconjunction with ISCA-36, June 2009.
2009-05-01 New PhD Student (Elnaz Ebrahimi)
2009-02-24 Measuring and Modeling Variability using Low-Cost FPGAs paper accepted
Michael Brown, Cyrus Bazeghi, Matthew Guthaus and Jose Renau, Poster at the International Symposium on Field-Programmable Gate Arrays (FPGA), February 2009.
2009-01-15 Sun Gift ($75K)

Gift to support thermal projects at the MASC group.

2008-07-16 Understanding bug fix patterns in verilog paper accepted
Sangeetha Sudakrishnan, Janaki T. Madhavan, E. James Whitehead Jr., Jose Renau, Fith International Workshop on Mining Software Repositories, May 2008.
2008-06-18 Implementation of a Power Efficient High Performance FPU for SCOORE paper accepted
Wael Ali Ashmawi, John Burr, Abhishek Sharma, Jose Renau, Workshop on Architectural Research Prototyping (WARP), held inconjunction with ISCA-35, June 2008.
2008-06-09 New thermal page

This page shows several of the thermal measurements performed by the MASC group

2008-06-08 New PhD Students (Gabriel Southern and Ehsan Ardestani)

Both would start in Fall 08

2008-09-24 Therminic conference call for papers
Papers are due on 2008-03-30.
More information on Therminic

International Workshop on Thermal inverstigations of ICs and Systems

2008-01-22 ICCAD conference call for papers
Papers are due on 2008-04-14.
More information on ICCAD

International Conference on Computer-Aided Design

2008-04-10 NSF CRI Infrared Equipment ($275K)

NSF Infrastructre award to purchase the IR measurement setup.

2008-01-12 New PhD Student (Alamelu)

Alamelu will start her PhD once she finishes the MS.

2008-04-01 Measuring Power and Temperature from Real Processors paper accepted
Francisco-Javier Mesa-Martinez, Michael Brown, Joseph Nayfach-Battilana, Jose Renau, The Next Generation Software (NGS) Workshop (NGS08) held in conjunction with IPDPS, April 2008.
2008-03-01 WACI paper accepted
uDSim, a Microprocessor Design Time Simulation Infrastructure. Sangeetha Sudhakrishnan, Francisco-Javier Mesa-Martinez, Jose Renau, Wild and Crazy Ideas VI (WACI) held in conjunction with ASPLOS, March 2008.

uDSim

2008-01-10 Processor Verification with hwBugHunt paper accepted
Sangeetha Sudhakrishnan, Liying Su, and Jose Renau, IEEE International Symposium on Quality Electronic Design (ISQED), March 2008.

First Sangeetha's paper, congratulations.

2008-02-01 Springer paper accepted
System and Processor Design Effort Estimation, Cyrus Bazeghi, Francisco J. Mesa-Martinez, and Jose Renau, Springer Research Trends in VLSI and Systems on Chip.

Mostly Cyrus thesis.

2008-01-10 nVIDIA Gift ($70K)

Gift to support thermal projects at the MASC group.

2007-10-10 NSF CSR Infrared Thermal Measurement ($300K)

Three years NSF grant for the thermal measurement infrastructure setup.

2007-10-04 PACT conference call for papers
Papers are due on 2008-03-20.
More information on PACT

Parallel Architectures and Compilation Techniques (PACT)

2007-08-23 New BLOG for the MASC group
2007-09-10 Effective Optimistic-Checker Tandem Core Design Through Architectural Pruning paper accepted
Francisco J. Mesa-Martinez and Jose Renau, 40th International Symposium on Microarchitecture (MICRO), December 2007.

Not a bad year for Javi, he has an ISCA and a MICRO.

2007-08-10 Estimating Design Time for System Circuits paper accepted
Cyrus Bazeghi, Francisco J. Mesa-Martinez, Brian Greskamp, Josep Torrellas, and Jose Renau, 15th IFIP International Conference on Very Large Scale Integration (VLSI-SoC), October 2007.
2007-07-01 Xilinx Equipment Donation

We have licenses to the latest Xilinx software tools.

2007-08-15 ISCA conference call for papers
Papers are due on 2007-11-09.
More information on ISCA

First-tier conference on computer architecture. This year, it is held on China.

2007-06-01 Javi Graduated

His thesis introduces a new methodology to improve processor efficiency by reducing the size of the codebase for a processor design in order to manage increases in complexity and extract further performance from already existing design. Based on this methodology he introduces a novel Tandem architecture which combines a complex out-of-order core, that has some of it underutilized functionality removed, with a verified simpler in-order core that guarantees forward progress whenever excised functionality from the complex processor is exercised.

2007-05-10 NASA/UARC "Radiation Tolerant FPGA Processor" ($25K)

Grant to continue supporting the development of the SCOORE project.

2007-05-01 Power Model Validation Through Thermal Measurements paper accepted
Francisco J. Mesa-Martinez, Joseph Nayfach-Battilan, and Jose Renau, International Symposium on Computer Architecture (ISCA), June 2007.
2007-05-01 Measuring Performance, Power, and Temperature from Real Processors paper accepted
Francisco J. Mesa-Martinez, Michael Brown, Joseph Nayfach-Battilana, and Jose Renau, 1st Workshop on Experimental Computer Science (FCRC), June 2007.
2007-02-02 SUN OpenSPARC Center of Excellence at Santa Cruz

Sun created the first ever OpenSPARC Center of Excellence at UCSC.

2007-02-01 SUN Academic Excellence Grant ($110K)

Sun donated $110K equipment to our group. Thanks Sun for this wonderful gift.

2006-09-01 SEED Scalable, Efficient Enforcement of Dependences paper accepted
Francisco J. Mesa-Martinez, Michael C.Huang, and Jose Renau, 15th International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2006.
2006-06-01 Printed Circuit Board Layout Time Estimation paper accepted
Cyrus Bazeghi and Jose Renau, 7th Workshop on Complexity-Effective Design (WCED), held in conjunction with ISCA-33, June 2006.
2006-06-01 SCOORE Santa Cruz Out-of-Order RISC Engine, FPGA Design Issues paper accepted
Francisco J. Mesa-Martinez, Abhishek Sharma, Andrew W. Hill, Carlos A. Cabrera, Cyrus Bazeghi, Hari Kolakaleti, Joseph Nayfach, Keertika Singh, Kevin S. Halle, Matthew D. Fischler, Melisa Nuñez, Sangeetha Nair, Suraj Narender Kurapati, Wael Ali Ashmawi, and Jose Renau , Workshop on Architectural Research Prototyping (WARP), held inconjunction with ISCA-33, June 2006.
2006-05-01 IES Berkeley/France Fund ($9K)

This small grant is shared with Albert Cohen from INRIA. The objective is to establish a collaboration between the two centers.

2006-03-01 Using Checkpoint-Assisted Value Prediction to Hide L2 Misses paper accepted
Luis Ceze, Karin Strauss, James Tuck, Jose Renau, and Josep Torrellas, ACM's Transactions on Architecture and Code Optimization (TACO), March 2006.
2006-03-01 POSH A TLS Compiler that Exploits Program Structure paper accepted
Wei Liu, James Tuck, Luis Ceze, Wonsun Ahn, Karin Strauss, Jose Renau and Josep Torrellas, ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), March 2006.
2006-02-01 Special Research Grant from UCSC ($12K)

Small explorative grant to rent/purchase equipment to get preliminary results on thermal projects.

2006-01-20 NASA/UARC "Checkpointed Fault Tolerant FPGA Systems" ($50K)

Grant to support the development of the SCOORE project.

2006-01-20 NSF CAREER ($400K)

The goal of this CAREER is to understand, estimate, and reduce processor design complexity. To do so, the PI plans to develop uComplexity metrics to understand and estimate processor design complexity. The uComplexity metric consist of three main parts, namely a procedure to account for the contributions of the different components in the design, accurate statistical regression of experimental measures using a nonlinear mixed-effects model, and a productivity adjustment to account for the productivities of different teams. Once the metrics are developed, the we plan to develop new approaches to reduce processor design complexity.

2006-01-01 Energy-Efficient Thread-Level Speculation on a CMP paper accepted
Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti Sarangi, James Tuck, and Josep Torrellas, IEEE Micro Special Issue Micro's Top Picks from Computer Architecture Conferences, January-February 2006.
2005-11-01 uComplexity Estimating Processor Design Effort paper accepted
Cyrus Bazeghi, Francisco J. Mesa-Martinez, and Jose Renau. 38th International Symposium on Microarchitecture (MICRO), November 2005.
2005-10-01 Sun grid donation of 100K CPU hours

Sun has donated 100K CPU on their sungrid project. We are not going to have CPU constraints the next year.

2005-10-01 Sun Niagara donation

Sun donated a Niagara (T1) machine to our group. Thanks for the support.

2005-09-01 POSH A Profiler-Enhanced TLS Compiler that Leverages Program Structure paper accepted
Wei Liu, James Tuck, Luis Ceze, Karin Strauss, Jose Renau, and Josep Torrellas. The Second Watson Conference on Interaction between Architecture, Circuits, and Compilers (P=AC2), September 2005.
2005-06-01 Thread-Level Speculation on a CMP Can Be Energy Efficient paper accepted
Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti Sarangi, James Tuck, and Josep Torrellas. International Conference on Supercomputing (ICS), June 2005.
2005-06-01 Tasking with Out-of-Order Spawn in TLS Chip Multiprocessors Microarchitecture and Compilation paper accepted
Jose Renau, James Tuck, Wei Liu, Luis Ceze, Karin Strauss, and Josep Torrellas. International Conference on Supercomputing (ICS), June 2005.
2005-04-01 Altera Equipment Donation

We have floating Quartus licenses.

2004-12-01 CAVA Hiding L2 Misses with Checkpoint-Assisted Value Prediction paper accepted
Luis Ceze, Karin Strauss, James Tuck, Jose Renau, and Josep Torrellas, IEEE TCCA Computer Architecture Letters (TCCA), Dec 2004.
2004-10-01 HPCS Complexity Management (Prime DoD/DARPA, Agency UIUC)

Small grant to purchase some equipment.

2004-07-01 UCSC Faculty Development award ($2K)

First small grant for our group.

2003-09-01 Managing Multiple Low-Power Adaptation Techniques The Positional Approach paper accepted
Michael Huang, Jose Renau and Josep Torrellas, Sidebar on Special Issue on Power-Aware Computing, (IEEE Computer), December 2003.
2003-06-01 Positional Adaptation of Processors Application to Energy Reduction paper accepted
Michael Huang, Jose Renau, and Josep Torrellas, International Symposium on Computer Architecture (ISCA), June 2003.
2003-06-01 Programming a Parallel Intelligent Memory System paper accepted
Basilio B. Fraguela, Jose Renau, Paul Feautrier, David Padua, and Josep Torrellas, Symposium on Principles and Practice of Parallel Programming (PPoPP), June 2003.
2002-11-01 Cherry Checkpointed Early Resource Recycling in Out-of-order Microprocessors paper accepted
Jose F. Martinez (Cornell University), Jose Renau (University of Illinois), Michael Huang (University of Rochester), Milos Prvulovic, and Josep Torrellas (University of Illinois), 35th International Symposium on Microarchitecture (MICRO), November 2002.
2002-08-01 Energy-Efficient Hybrid Wakeup Logic paper accepted
Michael Huang, Jose Renau, and Josep Torrellas, International Symposium on Low Power Electronics and Design (ISLPED), August 2002.
2002-06-01 A Framework for Dynamic Energy Efficiency and Temperature Management paper accepted
Michael Huang, Jose Renau, and Josep Torrellas Journal on Instruction Level Parallelism (JILP), 2002.
2001-12-01 Profiled-Based Energy Reduction for High-Performance Processors paper accepted
Wei Huang, Jose Renau, and Josep Torrellas, 4th ACM Workshop on Feedback-Directed and Dynamic Optimization, December 2001.
2001-06-01 Energy/Performance Design of Memory Hierarchies for Processor-In-Memory Chips paper accepted
Wei Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas, 2nd Workshop on Intelligent Memory Systems, November 2000, Lecture Notes in Computer Science(Vol. 2107) by Springer-Verlag, 2001.
2001-08-01 Cache Decomposition for Energy-Efficient Processors paper accepted
Michael Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas , International Symposium on Low Power Electronics and Design (ISLPED), August 2001.
2000-12-01 A Framework for Dynamic Energy Efficiency and Temperature Management paper accepted
Michael Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas, 33rd International Symposium on Microarchitecture (MICRO), December 2000.
2000-06-01 Memory Hierarchies in Intelligent Memories Energy/Performance Design paper accepted
Wei Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas, Ninth Workshop on Scalable Shared Memory Multiprocessors, June, 2000.