This website contains a set of open source tools developed and/or
partially maintained by the MASC group.
- liveHD:
LiveHD is an infrastructure designed for Live Hardware Development. By
live, we mean that small changes in the design should have the synthesis
and simulation results in a few seconds. LiveHD is optimized for synthesis
and simulation with a goal of supporting many hardware description
languages. It is available at livehd.
- dromajo:
dromajo started as a
class project for cmpe125 and soon afterwards Esperanto Tech pick it up as a
starting point to perform cosimulation for verification. The project was
open sourced, and there are several improvements since the release.
- ESESC:
ESESC is a cycle accurate architectural simulator. It models a very wide
set of architectures. You can think of ESESC as sesc 2.0 with many
enhancements.
- SESC:
SESC is the original unmaintained cycle accurate
architectural simulator. It models a very wide set of architectures: single
processors, CMPs, PIMs, and thread level speculation. Check the SESC website
at sesc.sourceforge.net.
- udsim:
Design complexity simulator. It uses a montecarlo approach modeling people
working on a CPU design project to estimate design times. Available at udsim.
- RUBY-VPI:
Ruby-VPI is a platform for unit
testing, rapid prototyping, and systems integration of Verilog modules
through the Ruby programming language. It has been develop by Suraj Kurapati
for his MS thesis. It was built to help the SCOORE verification and to explore
ideas on co-simulation.
- SCOORE:
Santa Cruz Out-of-Order Risc Engine. An out-of-order SPARC V8 processor.
This processor is synthesizable on FPGAs and ASIC.
- XCACTI:
XCACTI extended CACTI 3.2 cache power model. It uses a latch the sense
amplifier, and models different energies for read and writes. The
extensions have been used at the University of Illinois, University of
Rochester, North Carolina State University, U.C. Davis, U.C. Irvine, U.C.
Riverside, and University of Arizona.
It is available locally (xcacti.tgz), you can use
for any paper or work. Let me know if you find any problem or you publish a
paper using it.
- SCVTOOLS:
Santa Cruz Verilog Tools. As part of the SCOORE project two Verilog tools
have been developed: a coverage and a lint tool.
- HDLMETRICS:
HDL metrics is a GPL tool developed as a collaboration between UC-Santa
Cruz and University of Illinois. It reports a set of metrics for VHDL. The
source code is available in hdlmetrics.tgz
