Publications

• HDLEval Benchmarking LLMs for Multiple HDLs, Mark Zakharov, Farzaneh Rabiei Kashanaki, Jose Renau. The First IEEE International Workshop on LLM-Aided Design (ISLAD), July 2024.
• LLM Challenges Fixing Verilog Testbenches, Mark Zakharov, Farzaneh Rabiei Kashanaki, Alex Lee, Milind Varma, Jose Renau. The First IEEE International Workshop on LLM-Aided Design (ISLAD poster), July 2024.

• RETROSPECTIVE: Power model validation through thermal measurements, Jose Renau. ISCA@50 25-Year retrospective 1996-2020 (ISCA Retrospective), July 2023.
• A Multi-threaded Fast Hardware Compiler for HDLs, Sheng-Hong Wang, Hunter Coffman, Kenneth Mayer, Sakshi Garg, and Jose Renau. International Conference on Compiler Construction (CC), February 2023.

• Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation, Nursultan Kabylkas, Tommy Thorn (Esperanto Technologies), Shreesha Srinath (Intel), Polychronis Xekalakis (Nvidia), and Jose Renau. 54th International Symposium on Microarchitecture (MICRO), October 2021.
• Design Decisions in LiveHD for HDLs Compilation, Sheng-Hong Wang and Jose Renau, 1st Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE), April 2021.

• Load Driven Branch Predictor (LDBP), Akash Sridhar, Nursultan Kabylkas, Jose Renau, (arvix), September 2020.
• Live Hardware Development at UCSC, Jose Renau, Red Hat Research US 2020 (Talk), September 2020.
• LiveHD: A Productive Live Hardware Development Flow, Sheng-Hong Wang, Rafael T. Possignolo, Haven Blake Skinner, and Jose Renau, IEEE Micro magazine (MICRO Magazine), June 2020.
• LiveSim: A Fast Hot Reload Simulator, Haven Skinner, Rafael T. Possignolo, Sheng-Hong Wang, and Jose Renau, International Symposium on Performance Analysis of Systems and Software (ISPASS), April 2020.

• LGraph: A Unified Data Model and API for Productive Open-Source Hardware Design, Sheng-Hong Wang, Rafael T. Possignolo, Qian Chen, Rohan Ganpati, and Jose Renau, Second Workshop on Open-Source EDA Technology (WOSET), November 2019.
• LNAST: A Language Neutral Intermediate Representation for Hardware Description Languages, Sheng-Hong Wang, Akash Sridhar, and Jose Renau, Second Workshop on Open-Source EDA Technology (WOSET), 2019.
• EMI Architectural Model and Core Hopping, Daphne I. Gorman, Rafael T. Possignolo, and Jose Renau. 52th International Symposium on Microarchitecture (MICRO), October 2019.
• SMatch: Structural Matching for Fast Resynthesis in FPGAs, Rafael T. Possignolo, and Jose Renau, Design Automation Conference (DAC), June 2019.
• Live Graph infrastructure for Synthesis and Simulation, Jose Renau, Latch-Up conference (Latch-Up), May 2019.

• LGraph: A multi-language open-source database for VLSI, Rafael T. Possignolo, Sheng Hong Wang, Haven Skinner, and Jose Renau. First Workshop on Open-Source EDA Technology (WOSET), November 2018.
• GPU NTC Process Variation Compensation with Voltage Stacking, Rafael T. Possignolo, Elnaz Ebrahimi, Ehsan Ardestani, Alamelu Sankaranarayanan, Jose Luis Briz, Jose Renau. IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2018.
• Automating the Area-Delay Trade-off Problem, Haven Skinner, Rafael T. Possignolo, and Jose Renau. Second Workshop on Computer Architecture Research with RISC-V (CARRV), June 2018.
• Architectural Opportunities for Novel Dynamic EMI Shifting (DEMIS), Daphne I. Gorman, Jose Renau, and Matthew Guthaus. Top Picks Honorable Mention (Top Picks Honorable), May 2018.
• Securing Processors from Time Side Channels, Jose Renau. The Asilomar Microcomputer Workshop, April 2018.
• Securing Processors from Time Side Channels, Jose Renau. Open publication (Technical Report), April 2018.

• Automated Pipeline Transformations with Fluid Pipelines, Rafael T. Possignolo, Elnaz Ebrahimi, Haven Skinner, Jose Renau. Advanced Logic Synthesis (Book Chapter), December 2017.
• Liam: An Actor Based Programming Model for HDLs, Haven Skinner, Rafael T. Possignolo, and Jose Renau. 15th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE), October 2017.
• Architectural Opportunities for Novel Dynamic EMI Shifting (DEMIS), Daphne I. Gorman, Jose Renau, and Matthew Guthaus. 50th International Symposium on Microarchitecture (MICRO), October 2017.
• Rafael T. Possignolo and Elnaz Ebrahimi and Haven Skinner and Jose Renau. In Reis, André Inácio, Drechsler, Rolf (Eds.), Advanced Logic Synthesis (Springer), 2018.
• Anubis: A new benchmark for incremental synthesis, Rafael T. Possignolo, Nursultan Kabylkas, and Jose Renau, International Workshop Logic and Synthesis (IWLS), June 2017.
• LiveSynth: Towards an Interactive Synthesis Flow, Rafael T. Possignolo, and Jose Renau, Design Automation Conference (DAC), June 2017.
• Timing Speculative SRAM, Elnaz Ebrahimi, Matthew Guthaus, and Jose Renau, International Symposium on Circuits and Systems (ISCAS), May 2017.
• Level Shifter Design for Voltage Stacking, Elnaz Ebrahimi, Rafael T. Possignolo, and Jose Renau, International Symposium on Circuits and Systems (ISCAS), May 2017.

• LiveSynth: Towards an Interactive Synthesis Flow, Rafael T. Possignolo, Jose Renau, Hot Chips A Symposium on High Performance Chips (HotChips poster), August 2016.
• Overhead of Deoptimization Checks in the V8 JavaScript Engine, Gabriel Southern and Jose Renau, International Symposium on Workload Characterization (IISWC), July 2016.
• Fluid Pipelines: Elastic Circuitry meets Out-of-Order Execution, Rafael T. Possignolo, Elnaz Ebrahimi, Haven Skinner, and Jose Renau, International Conference on Computer Design (ICCD), June 2016.
• Fluid Pipelines: Elasticity without Throughput Penalty, Rafael T. Possignolo, Elnaz Ebrahimi, Haven Skinner, and Jose Renau, International Workshop on Logic and Synthesis (IWLS), April 2016.
• SRAM Voltage Stacking, Elnaz Ebrahimi, Rafael T. Possignolo, and Jose Renau, International Symposium on Circuits and Systems (ISCAS), May 2016.
• Analysis of PARSEC Workload Scalability, Gabriel Southern and Jose Renau, International Symposium on Performance Analysis of Systems and Software (ISPASS), April 2016.
• LiveSim: Going Live with Microarchitecture Simulation, Sina Hassani, Gabriel Southern and Jose Renau, International Symposium on High-Performance Computer Architecture (HPCA), February 2016.

• GPU NTC Process Variation Compensation with Voltage Stacking, Rafael T. Possignolo, Ehsan Ardestani, Alamelu Sankaranarayanan, Jose Luis Briz, Jose Renau, International Conference on Parallel Architectures and Compilation Techniques (PACT poster), October 2015.
• Deconstructing PARSEC Scalability, Gabriel Southern and Jose Renau, Workshop on Duplicating, Deconstructing and Debunking (WDDD), 2015.
• Managing Mismatches in Voltage Stacking with CoreUnfolding, Ehsan K. Ardestani, Rafael T. Possignolo, Jose Luis Briz, and Jose Renau, ACM's Transactions on Architecture and Code Optimization (TACO), September 2015.
• Section Based Program Analysis to Reduce Overhead of Detecting Unsynchronized Thread Communication, Madan Das, Gabriel Southern and Jose Renau, ACM's Transactions on Architecture and Code Organization (TACO), 2015.
• Section Based Program Analysis to Reduce Overhead of Detecting Unsynchronized Thread Communication, Madan Das, Gabriel Southern, and Jose Renau, 20th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP Poster), February 2015

• Deterministic Scaling, Gabriel Southern, Madan Das, and Jose Renau, Workshop on Determinism and Correctness in Parallel Programming (WODET), March 2013.
• Reducing Logging Overhead for Deterministic Execution, Madan Das, Gabriel Southern, and Jose Renau, Workshop on Determinism and Correctness in Parallel Programming (WODET), March 2013.
• Power Blurring: Fast Static and Transient Thermal Analysis Method for Packaged Integrated Circuits and Power Devices, Amirkoushyar Ziabari, Je-Hyoung Park, Ehsan K. Ardestani, Jose Renau, Sung-Mo Kang, and Ali Shakouri IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2013.
• ESESC A Fast Performance, Power, and Temperature Multicore Simulator, Ehsan K.Ardestani, Gabriel Southern, Jason Doung, Elnaz Ebrahimi, Jose Renau, Hot Chips A Symposium on High Performance Chips (HotChips poster), August 2013.
• An Energy Efficient GPGPU Memory Hierarchy with Tiny Incoherent Caches, Alamelu Sankaranarayanan, Ehsan K.Ardestani, Jose Luis Briz, and Jose Renau, International Symposium on Low Power Electronics and Design (ISLPED), September 2013.
• Sampling in Thermal Simulation of Processors: Measurement, Characterization, and Evaluation, Ehsan K.Ardestani, Francisco J. Mesa-Martinez , Gabriel Southern , Elnaz Ebrahimi , Jose Renau IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), August 2013.
• ESESC: A Fast Multicore Simulator Using Time-Based Sampling, Ehsan K.Ardestani, and Jose Renau, International Symposium on High-Performance Computer Architecture (HPCA), February 2013.

• Thermal-Aware Sampling in Architectural Simulation, Ehsan K.Ardestani, Elnaz Ebrahimi, Gabriel Southern, and Jose Renau, International Symposium on Low Power Electronics and Design (ISLPED), August 2012.
• Enabling Power Density and Thermal-Aware Floorplanning, Ehsan K. Ardestani, Amirkoushyar Ziabari, Ali Shakouri, and Jose Renau, 28th Annual Thermal Measurement, Modeling and Management Symposium (SEMITHERM), March 2012.

• ReRack: Power Simulation for Data Centers with Renewable Energy Generation, Michael Brown, and Jose Renau, GreenMetrics 2011,held in conjunction SIGMETRICS 2011, June 2011.
• Releasing Efficient Beta Cores to Market Early, Sangeetha Sudhakrishnan, Rigo Dicochea, and Jose Renau, International Symposium on Computer Architecture (ISCA), June 2011.
• Fast Thermal Simulators for Architecture Level Integrated Circuit Design, Amirkoushyar Ziabari, Ehsan K. Ardestani, Jose Renau, and Ali Shakouri, 27th Annual Thermal Measurement, Modeling and Management Symposium (SEMITHERM), March 2011.
• A Design Time Simulator for Computer Architects, Sangeetha Sudhakrishnan, Francisco J. Mesa-Martinez, and Jose Renau, IEEE International Symposium on Quality Electronic Design (ISQED), March 2011. (Best paper award)

• Real-time control for Keck Observatory next-generation adaptive optics, Marc Reinig, Donald Gavel, Ehsan Ardestani, Jose Renau, Proceedings of the SPIE, 2010.
• Characterizing Processor Thermal Behavior, Francisco J. Mesa-Martinez, Ehsan Ardestani, and Jose Renau, Fifteenth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2010.
• Cooling Solutions for Processor Infrared Thermography, Ehsan Ardestani, Francisco J. Mesa-Martinez, and Jose Renau, 26th Annual Thermal Measurement, Modeling and Management Symposium (SEMITHERM), February 2010.

• SOI, Interconnect, Package, and Mainboard Thermal Characterization, Joseph Nayfach-Battilana and Jose Renau, International Symposium on Low Power Electronics and Design (ISLPED), August 2009 (poster paper).
• Measuring and Modeling Variability using Low-Cost FPGAs, Michael Brown, Cyrus Bazeghi, Matthew R. Gutthaus, and Jose Renau, Workshop on Modeling, Benchmarking and Simulation (MOBS), held inconjunction with ISCA-36, June 2009.
• Measuring and Modeling Variability using Low-Cost FPGAs, Michael Brown, Cyrus Bazeghi, Matthew Guthaus and Jose Renau, Poster at the International Symposium on Field-Programmable Gate Arrays (FPGA), February 2009.

• Understanding bug fix patterns in verilog, Sangeetha Sudakrishnan, Janaki T. Madhavan, E. James Whitehead Jr., Jose Renau, Fith International Workshop on Mining Software Repositories, May 2008.
• Implementation of a Power Efficient High Performance FPU for SCOORE, Wael Ali Ashmawi, John Burr, Abhishek Sharma, Jose Renau, Workshop on Architectural Research Prototyping (WARP), held inconjunction with ISCA-35, June 2008.
• Measuring Power and Temperature from Real Processors, Francisco-Javier Mesa-Martinez, Michael Brown, Joseph Nayfach-Battilana, Jose Renau, The Next Generation Software (NGS) Workshop (NGS08) held in conjunction with IPDPS, April 2008.
• uDSim, a Microprocessor Design Time Simulation Infrastructure. Sangeetha Sudhakrishnan, Francisco-Javier Mesa-Martinez, Jose Renau, Wild and Crazy Ideas VI (WACI) held in conjunction with ASPLOS, March 2008.
• Processor Verification with hwBugHunt, Sangeetha Sudhakrishnan, Liying Su, and Jose Renau, IEEE International Symposium on Quality Electronic Design (ISQED), March 2008.
• System and Processor Design Effort Estimation, Cyrus Bazeghi, Francisco J. Mesa-Martinez, and Jose Renau, Springer Research Trends in VLSI and Systems on Chip.

• Effective Optimistic-Checker Tandem Core Design Through Architectural Pruning, Francisco J. Mesa-Martinez and Jose Renau, 40th International Symposium on Microarchitecture (MICRO), December 2007.
• Estimating Design Time for System Circuits, Cyrus Bazeghi, Francisco J. Mesa-Martinez, Brian Greskamp, Josep Torrellas, and Jose Renau, 15th IFIP International Conference on Very Large Scale Integration (VLSI-SoC), October 2007.
• Power Model Validation Through Thermal Measurements, Francisco J. Mesa-Martinez, Joseph Nayfach-Battilan, and Jose Renau, International Symposium on Computer Architecture (ISCA), June 2007.
• Measuring Performance, Power, and Temperature from Real Processors, Francisco J. Mesa-Martinez, Michael Brown, Joseph Nayfach-Battilana, and Jose Renau, 1st Workshop on Experimental Computer Science (FCRC), June 2007.

• SEED Scalable, Efficient Enforcement of Dependences, Francisco J. Mesa-Martinez, Michael C.Huang, and Jose Renau, 15th International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2006.
• Printed Circuit Board Layout Time Estimation, Cyrus Bazeghi and Jose Renau, 7th Workshop on Complexity-Effective Design (WCED), held in conjunction with ISCA-33, June 2006.
• SCOORE Santa Cruz Out-of-Order RISC Engine, FPGA Design Issues, Francisco J. Mesa-Martinez, Abhishek Sharma, Andrew W. Hill, Carlos A. Cabrera, Cyrus Bazeghi, Hari Kolakaleti, Joseph Nayfach, Keertika Singh, Kevin S. Halle, Matthew D. Fischler, Melisa Nuñez, Sangeetha Nair, Suraj Narender Kurapati, Wael Ali Ashmawi, and Jose Renau , Workshop on Architectural Research Prototyping (WARP), held inconjunction with ISCA-33, June 2006.
• Using Checkpoint-Assisted Value Prediction to Hide L2 Misses, Luis Ceze, Karin Strauss, James Tuck, Jose Renau, and Josep Torrellas, ACM's Transactions on Architecture and Code Optimization (TACO), March 2006.
• POSH A TLS Compiler that Exploits Program Structure, Wei Liu, James Tuck, Luis Ceze, Wonsun Ahn, Karin Strauss, Jose Renau and Josep Torrellas, ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), March 2006.
• Energy-Efficient Thread-Level Speculation on a CMP, Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti Sarangi, James Tuck, and Josep Torrellas, IEEE Micro Special Issue Micro's Top Picks from Computer Architecture Conferences, January-February 2006.

• uComplexity Estimating Processor Design Effort, Cyrus Bazeghi, Francisco J. Mesa-Martinez, and Jose Renau. 38th International Symposium on Microarchitecture (MICRO), November 2005.
• POSH A Profiler-Enhanced TLS Compiler that Leverages Program Structure, Wei Liu, James Tuck, Luis Ceze, Karin Strauss, Jose Renau, and Josep Torrellas. The Second Watson Conference on Interaction between Architecture, Circuits, and Compilers (P=AC2), September 2005.
• Thread-Level Speculation on a CMP Can Be Energy Efficient, Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti Sarangi, James Tuck, and Josep Torrellas. International Conference on Supercomputing (ICS), June 2005.
• Tasking with Out-of-Order Spawn in TLS Chip Multiprocessors Microarchitecture and Compilation, Jose Renau, James Tuck, Wei Liu, Luis Ceze, Karin Strauss, and Josep Torrellas. International Conference on Supercomputing (ICS), June 2005.

• CAVA Hiding L2 Misses with Checkpoint-Assisted Value Prediction, Luis Ceze, Karin Strauss, James Tuck, Jose Renau, and Josep Torrellas, IEEE TCCA Computer Architecture Letters (TCCA), Dec 2004.

• Managing Multiple Low-Power Adaptation Techniques The Positional Approach, Michael Huang, Jose Renau and Josep Torrellas, Sidebar on Special Issue on Power-Aware Computing, (IEEE Computer), December 2003.
• Positional Adaptation of Processors Application to Energy Reduction, Michael Huang, Jose Renau, and Josep Torrellas, International Symposium on Computer Architecture (ISCA), June 2003.
• Programming a Parallel Intelligent Memory System, Basilio B. Fraguela, Jose Renau, Paul Feautrier, David Padua, and Josep Torrellas, Symposium on Principles and Practice of Parallel Programming (PPoPP), June 2003.

• Cherry Checkpointed Early Resource Recycling in Out-of-order Microprocessors, Jose F. Martinez (Cornell University), Jose Renau (University of Illinois), Michael Huang (University of Rochester), Milos Prvulovic, and Josep Torrellas (University of Illinois), 35th International Symposium on Microarchitecture (MICRO), November 2002.
• Energy-Efficient Hybrid Wakeup Logic, Michael Huang, Jose Renau, and Josep Torrellas, International Symposium on Low Power Electronics and Design (ISLPED), August 2002.
• A Framework for Dynamic Energy Efficiency and Temperature Management, Michael Huang, Jose Renau, and Josep Torrellas Journal on Instruction Level Parallelism (JILP), 2002.

• Profiled-Based Energy Reduction for High-Performance Processors, Wei Huang, Jose Renau, and Josep Torrellas, 4th ACM Workshop on Feedback-Directed and Dynamic Optimization, December 2001.
• Energy/Performance Design of Memory Hierarchies for Processor-In-Memory Chips, Wei Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas, 2nd Workshop on Intelligent Memory Systems, November 2000, Lecture Notes in Computer Science(Vol. 2107) by Springer-Verlag, 2001.
• Cache Decomposition for Energy-Efficient Processors, Michael Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas , International Symposium on Low Power Electronics and Design (ISLPED), August 2001.

• A Framework for Dynamic Energy Efficiency and Temperature Management, Michael Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas, 33rd International Symposium on Microarchitecture (MICRO), December 2000.
• Memory Hierarchies in Intelligent Memories Energy/Performance Design, Wei Huang, Jose Renau, Seung-Moon Yoo, and Josep Torrellas, Ninth Workshop on Scalable Shared Memory Multiprocessors, June, 2000.