We are ready to release ESESC in beta version. For the moment, we will provide the source code under request. Once it has been tested by several users outside UCSC, we plan to create a git repository.

ESESC provides a toolchain to evaluate performance, power, energy, and thermal trade-offs at architectural level.

Features

• It is very fast (around 10MIPS with sampling)

• Uses QEMU and supports user mode ARM ISA

• Models OoO and InOrder cores in detail (ROB, Instruction Window, etc)

• Supports configurable memory hierarchy, and on-chip memory controller

• Supports multicore, homogeneous and heterogeneous configurations

• Simulates multithreaded and multiprogram applications

• Models power and temperature in addition to performance, and their interactions

Compared against SESC

ESESC is a significant evolution/improvement over sesc:

• ESESC has ARM ISA, sesc had MIPS ISA.

• ESESC can run unmodified Linux ARM binaries, MIPS required a custom toolchain.

• ESESC uses QEMU for emulation, sesc had a custom emulator.

• ESESC is integrated with McPat, sesc had an older Wattch model.

• ESESC has a brand new memory hierarchy, sesc had a more complex coherence.

• ESESC has improved thermal modeling, sesc had HotSpot

• ESESC has many types of sampling (statistical, smarts, simpoint), sesc had none.

• ESESC is actively maintained, sesc is no longer mantained.

• ESESC has many bugs solved.

Download

ESESC is currently is in its beta state, and the stable source code will be released and announced in this page soon. If you would like to try the beta version, please send us an email.

ESESC is first introduced in the HPCA 2013 paper ESESC: A Fast Multicore Simulator Using Time-Based Sampling by Ehsan K.Ardestani, and Jose Renau. This paper is the first to propose the concept of Time-Based Sampling (TBS) to solve the issues related to evaluation of multithreaded applications.

Abstract

Architects rely on simulation in their exploration of the design space. However, slow simulation speed caps their productivity and limits the depth of their exploration. Sampling has been a commonly used remedy. While sampling is shown to be an effective technique for single core processors, its application has been limited to simulation of multiprogram, throughput applications only. This work presents Time-Based Sampling (TBS), a framework that is the first to enable sampling in simulation of multicore processors with virtually no limitation in terms of application type (multiprogrammed or multithreaded), number of cores, homogeneity or heterogeneity of the simulated configuration (4.99% error averaged across all the evaluated configurations). TBS also is the first to enable integrated power and temperature evaluation in statistically sampled simulation of multicore systems (with 5.5% and 2.4% error on average, respectively). We implement an architectural simulator based on TBS, called ESESC, that provides a holistic set of tools for a fair evaluation of different architectures.

ESESC is used by the ISLPED 2012 paper Thermal-Aware Sampling in Architectural Simulation by Ehsan K.Ardestani, Elnaz Ebrahimi, Gabriel Southern, and Jose Renau explains how to perform thermal sampling with ESESC for a single core configuration.

Abstract

Thermal behavior of modern processors is a first-order design constraint. However, accurate estimation of thermal behavior is time consuming, and techniques for accelerating performance simulations often yield inaccurate results when directly applied to thermal simulation, or do not reduce the thermal computation at all. This paper is the first to propose thermal sampling techniques. It can be integrated with existing phase-based and statistical-based architectural simulator sampling. The resulting simulator can perform accurate performance, power, and thermal characterization at close to 30 MIPS, on average, instead of 5 MIPS for the fastest sampling technique without thermal-aware.