Tutorial Goals
The full day tutorial held on December 7th at MICRO 2013 will cover an introduction of the main ESESC components. It is designed for PhD students and industry researchers to get a fast introduction to ESESC and show some sample projects and advanced features.
What is ESESC?
ESESC is a fast multiprocessor simulator with detailed power, thermal, and performance models for modern out-of-order multicores. ESESC is an evolution of the popular SESC simulator (Enhanced SESC) that provides many new features.
The main ESESC characteristics are the following:
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It is very fast (over 20MIPS with sampling)
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Uses QEMU and supports user mode ARM ISA
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Models OoO and InOrder cores in detail (ROB, Instruction Window, etc)
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Supports configurable memory hierarchy, and on-chip memory controller
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Supports multicore, homogeneous and heterogeneous configurations
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Simulates multithreaded and multiprogram applications
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Models power and temperature in addition to performance, and their interactions
ESESC is a significant evolution/improvement over SESC:
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ESESC has ARM ISA, sesc had MIPS ISA.
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ESESC can run unmodified Linux ARM binaries, MIPS required a custom toolchain.
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ESESC uses QEMU for emulation, sesc had a custom emulator.
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ESESC is integrated with McPat, sesc had an older Wattch model.
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ESESC has a brand new memory hierarchy, sesc had a more complex coherence.
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ESESC has improved thermal modeling, sesc had HotSpot
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ESESC has many types of sampling (statistical, smarts, simpoint), sesc had none.
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ESESC is actively maintained, sesc is no longer mantained.
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ESESC has many bugs solved.
Tutorial Program (slides and demo instructions)
The schedule for the tutorial is listed below:
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08:00 - 09:00: Breakfast
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09:00 - 09:30: Overview
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09:30 - 10:30: Code Structure and Tools
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10:30 - 11:00: Morning Break
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11:00 - 12:00: Timing Model
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12:00 - 12:30: Sampling Methods Part 1
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12:30 - 13:30: Lunch
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13:30 - 14:15: Sampling Methods Part 2
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14:15 - 15:00: Power Model
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15:00 - 15:30: Afternoon Break
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15:30 - 16:30: Thermal Model
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16:30 - 17:00: Wrap-up