We are ready to release ESESC in beta version. For the moment, we will provide the source code under request. Once it has been tested by several users outside UCSC, we plan to create a git repository.

ESESC provides a toolchain to evaluate performance, power, energy, and thermal trade-offs at architectural level.


  • It is very fast (around 10MIPS with sampling)

  • Uses QEMU and supports user mode ARM ISA

  • Models OoO and InOrder cores in detail (ROB, Instruction Window, etc)

  • Supports configurable memory hierarchy, and on-chip memory controller

  • Supports multicore, homogeneous and heterogeneous configurations

  • Simulates multithreaded and multiprogram applications

  • Models power and temperature in addition to performance, and their interactions

Compared against SESC

ESESC is a significant evolution/improvement over sesc:

  • ESESC has ARM ISA, sesc had MIPS ISA.

  • ESESC can run unmodified Linux ARM binaries, MIPS required a custom toolchain.

  • ESESC uses QEMU for emulation, sesc had a custom emulator.

  • ESESC is integrated with McPat, sesc had an older Wattch model.

  • ESESC has a brand new memory hierarchy, sesc had a more complex coherence.

  • ESESC has improved thermal modeling, sesc had HotSpot

  • ESESC has many types of sampling (statistical, smarts, simpoint), sesc had none.

  • ESESC is actively maintained, sesc is no longer mantained.

  • ESESC has many bugs solved.


ESESC is currently is in its beta state, and the stable source code will be released and announced in this page soon. If you would like to try the beta version, please send us an email.